Inverter

Using an inverter-free solution to attenuate the PWM DAC output ripple and achieve nearly the same ripple performance and nearly-as-fast settling time as ...

The resulting output signal—with the same 30Tpwm settling time as Figure 4—is shown in Figure 6. Its ~25Tpm settling is encroaching on twice the speed of Figure 1’s original dual RC’s 41Tpm without compromising 1 lsb Vrpp. This results in the final ripple signal being delayed by a half-cycle and therefore inverted relative to the original PWM, which makes a simple passive summation equivalent to subtraction. In all, a total of 64 submissions have been accepted since his first contribution was published in 1974. It gives a Vrpp (ripple peak-to-peak amplitude expressed as a fraction of full-scale) of ~Tpwm / 4RC, where Tpwm = PWM cycle time, for the worst case of a 50% duty cycle. Clearly any desired degree of ripple attenuation can be achieved by making RC long enough (e.g., RC = 64Tpwm for Vrpp = 1/28 = one 8-bit lsb), but DAC response time will correspondingly suffer: